In semiconductor processing, features are fabricated on semiconductor substrates in a cleanroom environment using processing recipes that have many processing steps. A cluster system, which integrates a number of process chambers to perform sequential processing steps without removing substrates from a highly controlled processing environment, is generally used in processing semiconductor substrates.
Many photolithographic cluster systems used in the manufacturing of semiconductor integrated circuits currently incorporate an integrated wafer track and photolithographic system. Various modules within the wafer lithographic cluster perform certain functions including the coating of an underlying semiconductor wafer substrate with photosensitive films referred to as photoresists or resists. In current track systems, the lithography tool is typically directly connected to tracks that take care of both the input processes (e.g., applying the resist) as well as the output processes (e.g., post expose bake/chill and development).
Electronic device manufacturers often spend a large amount of time trying to optimize the process sequence and chamber processing time to achieve the greatest substrate throughput possible given the cluster tool architecture limitations and the chamber processing times. In general, the longest process recipe step generally limits the throughput of the processing sequence.
In addition, certain process steps have stringent time variation requirements. Two such exemplary processing steps include a post exposure bake (PEB) step and a post-PEB chill step. The PEB step is used to heat a substrate immediately after exposure to stimulate diffusion of the photoactive compounds and reduce the effects of standing waves in the photoresist layer. The post-PEB chill step generally cools the substrate after the PEB step to a temperature at or near ambient temperature to assure that the substrate is at a defined temperature, and is typically controlled so that each substrate sees the same time-temperature profile to minimize process variability. The PEB step typically must be linked tightly to the lithography step because variation in the timing between the expose process of the lithography step and the PEB step impacts the Critical Dimension Uniformity (CDU) of the final product.
Similarly, the slowest wafer on either the input or output branch determines the processing time for each lot (i.e., a group of wafers which are to be processed in the same way) in the track. For example, in some cases, if a fast lot is followed by a slow lot, which is followed by a fast lot, each of the lots will run at the speed of the slow lot from the time the slow lot enters the track until the slow lot leaves the track. Similarly, in some other cases, the track schedules around the slowest lot. As a result, the track lets the fast lot run normally, accepting that the slow lot will (partially) empty the track. Thereafter, the track waits to start the fast lot until the slow lot will not stall wafers of the following fast lot. In either situation, the throughput of the entire track-lithography cluster is reduced.